The invention relates to a synchronous circuit, such as a synchronous integrated memory. Synchronous memories, for example synchronous DRAMs (SDRAMs) or Rambus DRAMs (RDRAMs), have data connections via which data are transmitted in synchronism with a first clock signal transmitted by a control unit, such as a controller. At relatively high frequencies ( greater than 200 MHz), it is necessary for the synchronous memory to generate a second clock signal which is synchronous with the first clock signal and is used to control the synchronous data transmission from or to the memory.
Sidiropoulos and Horowitz, in xe2x80x9cSemidigital Dual Delay-Locked Loopxe2x80x9d, IEEE Journal of Solid State Circuits, Vol. 32 No. 11, November 1997, p. 1683 et seq., describe how an output clock signal which is synchronous with an input clock signal is generated using a two-stage DLL (delay locked loop) circuit. A first phase locked loop (core DLL) generates from the input clock signal six intermediate clock signals each phase-shifted by 30xc2x0 with respect to one another. A second phase locked loop (peripheral DLL) connected downstream of the first control loop generates the output clock signal by interpolating two respective adjacent intermediate clock signals.
The DLL circuit proposed by Sidiropoulos and Horowitz is thus controlled in two stages:
In the first control loop, the phase angle of the intermediate clock signals is controlled to exactly 30xc2x0 in each case, and in the second control loop, the phase angle of the output clock signal is controlled, so that it is subsequently in phase with the input clock signal. For performing the interpolation, to generate the output clock signal on the basis of the phase error established with respect to the input clock signal, the second control loop then always selects those of the intermediate clock signals adjacent in terms of phase which are best suited to this purpose. If, by way of example, relatively large changes in temperature cause phase errors in the intermediate clock signals with respect to their nominal values, the first control loop effects a readjustment. This readjustment can sometimes result in an abrupt change in the phase angle of the intermediate clock signals. Since the second control loop always uses two of these intermediate clock signals for its interpolation, these abrupt changes result in likewise abrupt changes in the output clock signal generated by the second control loop.
It is accordingly an object of the invention to provide a synchronous circuit, which overcomes the above-mentioned disadvantages of the heretofore-known devices and methods of this general type, in which a clock generator is used to generate from a first clock signal a second clock signal which is synchronous with the latter and is used to control the data transmission by means of an output driver and/or an input driver. In this context, the second clock signal is intended to be as phase-locked as possible with respect to the first clock signal, but the data transmission by means of the driver is intended not to be subject to any abrupt changes in the second clock signal.
With the foregoing and other objects in view there is provided, in accordance with the invention, a synchronous circuit, comprising:
a clock input for receiving a first clock signal;
a clock signal generator for generating a second clock signal, the clock signal generator being phase-locked with respect to the first clock signal, having an input connected to the clock input, and having a clock output for outputting the second clock signal;
a data transmission unit for one of outputting data from an integrated circuit and reading data into the integrated circuit substantially in synchronism with the first clock signal;
the data transmission unit having a control input connected to the clock output of the clock signal generator;
the clock signal generator having at least two control loops connected in series for controlling a phase angle of the second clock signal, the at least two control loops including a first control loop for generating from the first clock signal at least two intermediate clock signals each having a particular phase angle with respect to the first clock signal, and a second control loop for generating the second clock signal from the intermediate clock signals; and
a deactivation unit connected to the first control loop for deactivating a control of the first control loop during a transmission of data by the data transmission unit, such that a control of the phase angles of the intermediate clock signals is interrupted and corresponding control signals for setting the phase angles are kept constant.
The synchronous circuit may, by way of example, be a synchronous memory or a processor. The fundamental aspect is merely that the circuit is used for data transmission in synchronism with a first clock signal.
The synchronous integrated circuit has a clock input for supplying a first clock signal and a clock generator for generating a second clock signal, which is phase-locked with respect to the first clock signal. This means that the two clock signals have a fixed phase relationship with respect to one another. The clock generator has an input which is connected to the clock input, and a clock output for outputting the second clock signal, said output being connected to a control input of a data transmission unit used for outputting data from the circuit and/or for reading data into the circuit essentially in synchronism with the first clock signal. The clock generator has at least two control loops connected in succession which are used for controlling the phase angle of the second clock signal, the first control loop being used to generate from the first clock signal at least two intermediate clock signals, each of which has a particular phase angle with respect to the first clock signal, and the second control loop being used to generate the second clock signal from the intermediate clock signals. In addition, the circuit has a deactivation unit for deactivating the control of the first control loop during the transmission of data by the data transmission unit, so that the control of the phase angle of the intermediate clock signals is interrupted and corresponding control signals for setting these phase angles are kept constant.
The fact that the control of the first control loop is deactivated during the transmission of data means that no abrupt changes in the phase angles of the intermediate clock signals arise during the data transmission. There are therefore also no otherwise arising abrupt changes in the phase angle of the second clock signal which the second control loop would again first need to correct. If, on the other hand, no data are being transmitted by the data transmission unit, abrupt changes in the phase angle of the intermediate clock signals and of the second clock signal are not critical, since the second clock signal is not required for controlling the data transmission unit in these periods of time. The control of the first control loop can therefore always be activated if no data are to be transmitted by the data transmission unit. Since, in normal operation, there is always alternation between periods of time in which data are transmitted and periods of time in which no data are to be transmitted, the phase angles of the intermediate clock signals are accurately readjusted whenever the first control loop is newly activated.
The data transmission unit may be an input and/or output circuit of the synchronous circuit.
Phase drift in the intermediate clock signals is primarily initiated by fluctuations in temperature during operation of the circuit. Relatively large fluctuations in temperature take place only within relatively long periods of time, however. It is therefore not critical for the first control loop to be deactivated during the periods of time over which the data transmission takes place, which are generally relatively short in this context. Since the second control loop remains activated during the data transmission, provision is also made for adequate correction of lesser interference during the data transmission.
The clock generator can, by way of example, be in the same form as the two-stage DLL circuit described in the above-mentioned article by Sidiropoulos and Horowitz. Its first control loop then generates from the first clock signal a plurality of intermediate clock signals phase-shifted with respect to one another by the same phase angle in each case, and its second control loop generates the second clock signal by means of interpolation between two respective intermediate clock signals which are adjacent in terms of phase.
In accordance with an added feature of the invention:
the first control loop generates from the first clock signal a plurality of intermediate clock signals phase-shifted with respect to one another by the same angle in each case; and
the second control loop produces the second clock signal by interpolation between two respective intermediate clock signals positioned adjacent in terms of phase.
In accordance with an additional feature of the invention:
the first control loop has a phase detector for ascertaining the phase difference between at least one of the intermediate clock signals and the first clock signal;
the first control loop is configured to set the control signals in dependence on an output signal from the phase detector; and
the first control loop includes a memory unit for storing the control signals, and wherein a memory content of the memory unit is continually changed when the control of the first control loop has been activated and the memory content remains constant when the control of the first control loop has been deactivated.
The first control loop, in this development, has a phase detector for ascertaining the phase difference between at least one of the intermediate clock signals and the first clock signal. The first control loop sets its control signals, which are used for setting the phase angles of the intermediate clock signals, on the basis of an output signal from the phase detector. In addition, the first control loop has a memory unit for storing the control signals, whose memory content is continually changed when the control of the first control loop has been activated and whose memory content remains constant when the control of the first control loop has been deactivated.
The memory unit advantageously ensures that the control signals are kept constant during the deactivation of the first control loop, that is to say during the data transmission by the data transmission unit.
In accordance with another feature of the invention, an external control unit is connected to the deactivation unit via an input. The external control unit controls the data transmission by the data transmission unit and outputs a control signal to the deactivation unit for deactivating the control of the first control loop in dependence on the control signal.
In accordance with a concomitant feature of the invention, an external control unit is connected to an output and receives therefrom a control signal controlling the data transmission by the data transmission unit. The control signal indicates whether or not the first control loop has been deactivated by the deactivation unit.
In the embodiment of the synchronous circuit that has an input for receiving a control signal from an external control unit used for controlling the data transmission by the data transmission unit, the deactivation unit of the memory deactivates the control of the first control loop on the basis of the control signal. If the synchronous circuit is a synchronous memory, the control unit may be a controller or microprocessor, for example, which controls the transmission of data by means of the data transmission unit by addressing the memory. Since, in this case, the external control unit stipulates when data transmission is to take place, it can easily also be used to transmit the appropriate control signal to the deactivation unit, so that the first control loop is deactivated at the same time as the data transmission which is to take place.
In the alternative embodiment in which the circuit has an output for transmitting a control signal to an external control unit used for controlling the data transmission by the data transmission unit, the control signal indicates whether the first control loop has been deactivated by the deactivation unit. This embodiment is advantageous if the circuit deactivates its first control loop independently of the external control unit by activating and deactivating the first control loop at stipulated time intervals, for example. These time intervals can be proportioned such that the intermediate clock signals are controlled with sufficient accuracy by the first control loop, and relatively large phase errors are prevented. The control signal transmitted to the external control unit indicates to the latter when the data transmission by means of the data transmission unit can be started, because the first control loop has then been deactivated, and when no data can be transmitted, because the first control loop is currently active.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a synchronous circuit, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.